X Congreso de la Sociedad Internacional de Peritos en Documentoscopia

Title: "Time Predictability and Composability in High-Performance Mixed-Criticality Multicore Systems."

• Biografía

  Francisco J. Cazorla is a researcher at the National Spanish Research Council (CSIC). He is currently the leader of the group on Interaction between the Operating System and the Computer Architecture at Barcelona Supercomputing Centre (http://www.bsc.es/caos). His research area focuses on multithreaded architectures for both high-performance and real-time systems. He has co-authored over 100 papers in inter- national refereed conferences. He has participated in several projects with industry including several proces- sor vendor companies (IBM, Sun microsystems) and European FP6 (SARC) and FP7 Projects (MERASA, parMERASA, SAFURE, PROARTIS). He currently leads the PROXIMA project and one project with the European Space Agency.

• Resumen

  The fundamental paradigms for the definition of Critical-Real Time Embedded Systems (CRTES) architectures are changing due to cost pressure, flexibility, extensibility and the demand for increased func- tional complexity. CRTES have been based on the federated architecture paradigm, which simplifies verifi- cation by providing a separation of responsibilities, hence enabling each provider to implement the hardware and software for a particular function independently from other suppliers. However, implementing an in- creasing amount of functionality on a Federated Architecture requires a high number of hardware units, mak- ing federated implementations inefficient in terms of size, weight and power consumption.

  To cope with such problem, the automotive and avionics industries are adopting Integrated Architectures (IA). One fundamental requirement of integrated architectures is to ensure that incremental qualification (verification) is possible, whereby each software partition can be subject to verification and validation – including timing analysis – in isolation, independent of the other partitions, with obvious benefits for cost, time and effort. In this talk I will focus on the timing component of incremental qualification. I will present some hardware support that can enable composability while providing high performance. I will also talk about existing soft- ware support to increase time predictability and time composability. I will also talk about the feasibility of a probabilistic timing analysis approach, and the hardware support required in order to enable it, as a way to provide high performance and time composability.